module store_unit(
  input [3:0] op,
  input [63:0] src1,
  input [63:0] src2,
  input [63:0] imm,

  output [63:0] addr,
  output [63:0] data,
  output [3:0] bytes,
  output valid_o

);
  /*verilator no_inline_module*/ 
wire op_sd/*verilator public_flat*/ ,op_sw/*verilator public_flat*/ ,op_sh/*verilator public_flat*/ ,op_sb /*verilator public_flat*/ ;
assign {op_sd,op_sw,op_sh,op_sb} = op;
assign bytes = {op_sd,op_sw,op_sh,op_sb};
assign addr = src1 + imm;
assign data = src2;
assign valid_o = |op;
endmodule
